1. Field of the Invention
The invention relates to integrated circuit fabrication, and more particularly to logic synthesis techniques that have increased tolerance to build variations.
2. Description of Related Art
An integrated circuit design flow typically proceeds through the following stages: product idea, electronic design automation (EDA), tape-out, fabrication, packing/assembly, and chips. The EDA software stage typically includes steps of System Design, Logic Design and Functional Verification, Synthesis and Design for Test, Design Planning, Netlist Verification, Physical Implementation, Analysis and Extraction, Physical Verfication (DRC, LRC, LVS), Resolution Enhancement (OPC, PSM, Assists), and Mask Data Preparation.
Logic synthesis typically begins with a logic design which specifies the various functional blocks that are to be implemented on the integrated circuit, and a “netlist” that indicates the electrical interconnections that are to be made between outputs of each block and inputs of the next. The functional blocks are typically specified in terms of standard cell functions available in a library provided by a fabrication vendor, which are specific to the vendor's fabrication process technology. For most cell functions the library offers a number of different cells optimized for different purposes. It is primarily a task of logic synthesis to select the optimum cell from the library. The selection is usually made on the basis of factors such as minimum and maximum setup and hold times, chip area occupied, and leakage current, and it is an iterative process to select cells that optimize over an entire module or chip.
As chip designers begin preparing designs for the 28 and 20 nm technology nodes and below, however, circuit behavior is becoming increasingly unpredictable. Aspects of the invention address this problem.